VLSI Design and Testing

My research interests include design for test and fault tolerance for VLSI designs, including MultiProcessor System-on-Chip (MPSoCs) and Network-on-Chip (NoC). This research is developed in cooperation with Grupo de Apoio ao Projeto de Hardware - GAPH.

Here is a lists os research topics and current design projects I am involved.

Research Projetcs

• Fault tolerant MPSoC;
• Publish/subscribe programing for MPSoCs;
• Testable resilient architetures;
• Control theory for self-adaptable MPSoC;

Current Students

Former Students

• Leonardo Rezende Juracy (PhD student); Currently advised by prof Fernando Moraes;
• Paulo Vancin (PhD student); Currently advised by prof Ney Calazans;
• Anderson Domingues (MSc); ORCA: a self-adaptive, multiprocessor system-on-chip platform. with honors;
• Jean Hamerski (PhD); support to run-time adaptation by a publish-subscribe based middleware for mpsoc architectures;
• Felipe Kuentzer (PhD). More than a timing resilient template: a case study on reliability-oriented improvements on Blade;
• Eduardo Wacther (PhD). Layered approach for runtime fault recovery in NOC-Based MPSOCS;
• Leonardo Rezende Juracy (MsC). Testing The Blade Resilient Asynchronous Template: A Structural Approach;
• Marcelo Grandi Mandelli (MsC). Mapeamento dinâmico de aplicações para MPSOCS homogêneos;
• Francisco Barreto (MsC). Tolerância a Falhas em Elementos de Processamento de MPSoCs;
• Walter Lau Neto (Computer Engineering student);

Main Resources

• HeMPS MPSoC;
• BLADE asynchronous resilient template;